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_______________ge ne ra l de sc ript ion the max152 high-speed, microprocessor (p)-com- patible, 8-bit analog-to-digital converter (adc) us es a half-flash technique to achieve a 1.8s conversion time, and digitizes at a rate of 400k samples per s ec- ond (ksps). it operates with single +3v or dual 3 v supplies and accepts either unipolar or bipolar inp uts. a C p o w e r d o w n C pin reduces current consumption to a typical value of 1a. the part returns from powe r- down and acquires an input signal in less than 900n s, providing large reductions in supply current in app lica- tions with burst-mode input signals. the max152 is dc and dynamically tested. its p in ter- face appears as a memory location or input/output p ort that requires no external interface logic. the data out puts use latched, three-state buffered circuitry for direct connection to a p data bus or system input port. the adc's i nput/ref- erence arrangement enables ratiometric operation. a fully- assembled evaluation kit provides a proven pc board lay- out to speed prototyping and design. _______________________applic a t ions cellular telephones portable radios battery-powered systems burst-mode data acquisition digital signal processing telecommunications high-speed servo loops ___________________________fe a t ure s ? single +3.0v to +3.6v supply ? 1.8s conversion time ? power-up in 900ns ? internal track/hold ? 400ksps throughput ? low power: 1.5ma (operating mode) 1a (power-down mode) ? 300khz full-power bandwidth ? 20-pin dip, so and ssop packages ? no external clock required ? unipolar/bipolar inputs ? ratiometric reference inputs ? 2.7v version available C contact factory ______________orde ring i nform a t ion * contact factory for dice specifications. ** contact factory for availability and processing t o mil-std-883. m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v dd v ss pwrdn d7 (msb) d6 d5 d4 cs vref+ vref- v in d0 (lsb) d1 d2 d3 wr /rdy mode rd int gnd dip/so/ssop max152 __________________pin configura t ion top view three- state drivers 4-bit dac 4-bit flash adc 4-bit flash adc (4lsb) d0-d7 data out pins 2-5, 14-17 vref+ vref- v in 12 11 1 pwrdn 18 20 v dd 10 wr /rdy cs gnd 7 6 13 89 19 rd int v ss mode max152 timing and control circuitry vref+ 16 ________________func t iona l dia gra m ca ll t oll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 for fre e sa m ple s or lit e ra t ure . part temp. range max152cpp 0c to +70c MAX152CWP 0c to +70c max152cap 0c to +70c max152c/d 0c to +70c max152epp -40c to +85c max152ewp -40c to +85c max152eap -40c to +85c max152mjp -55c to +125c pin-package 20 wide so 20 ssop dice* 20 plastic dip 20 wide so 20 ssop 20 cerdip** 20 plastic dip 19-0119; rev. 1; 12/93 evaluation kit manual follows data sheet downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n 2 _______________________________________________________________________________________ v dd to gnd ............................................. ................-0.3v to +7v v ss to gnd ............................................. .................+0.3v to -7v digital input voltage to gnd ....................... .-0.3v, (v dd + 0.3v) digital output voltage to gnd .....................- 0.3v, (v dd + 0.3v) vref+ to gnd................................(v ss - 0.3v) to (v dd + 0.3v) vref- to gnd.................................(v ss - 0.3v) to (v dd + 0.3v) v in to gnd .....................................(v ss - 0.3v) to (v dd + 0.3v) continuous power dissipation (t a = +70c) plastic dip (derate 11.11mw/c above +70c) ......... .889mw wide so (derate 10.00mw/c above +70c)............. .800mw ssop (derate 8.00mw/c above +70c) ................. ...640mw cerdip (derate 11.11mw/c above +70c) ............. ..889mw operating temperature ranges: max152c__ .......................................... ..............0c to +70c max152e__ .......................................... ...........-40c to +85c max152mjp .......................................... ........-55c to +125c storage temperature range .......................... ...-65c to +150c lead temperature (soldering, 10sec) ................ .............+300c electrical characteristics (unipolar input range, v dd = 3.0v to 3.6v, gnd = 0v, v ss = gnd, vref+ = 3.0v, vref- = gnd, specifications ar e given for rd mode (pin 7 = gnd), t a = t min to t max , unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. parameter symbol conditions units resolution n bits total unadjusted error tue unipolar range lsb differential nonlinearity dnl no-missing-codes guaranteed lsb zero-code error (note 2) unipolar and bipolar modes lsb full-scale error (note 2) unipolar and bipolar modes lsb s/(n+d) max152c/e, f sample = 400khz, f in = 30.273khz db thd db spurious-free dynamic range db input full-power bandwidth v in = 3.0v p-p mhz maximum input slew rate, tracking v/s input voltage range v in v input leakage current i in v ss < v in < v dd a input capacitance c in pf reference resistance rref k vref+ input voltage range v vref- input voltage range v signal-to-noise plus distortion ratio total harmonic distortion max152m, f sample = 340khz, f in = 30.725khz max152c/e, f sample = 400khz, f in = 30.273khz max152m, f sample = 340khz, f in = 30.725khz absolute maximum ratings max152c/e, f sample = 400khz, f in = 30.273khz max152m, f sample = 340khz, f in = 30.725khz min typ max 8 1 1 1 1 -50 -50 50 50 0.3 0.28 0.5 vref- vref+ 3 22 12 4 vref- v dd v ss vref+ 45 45 dynamic performance (note 3) accuracy (note 1) analog input reference input downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n _______________________________________________________________________________________ 3 parameter conditions units cs , wr , rd , pwrdn 2.0 input high voltage v inh mode 2.4 v cs , wr , rd , pwrdn 0.66 input low voltage v inl mode 0.8 v cs , rd , pwrdn 1 wr 3 input high current i inh mode 15 100 a input low current i inl cs , wr , rd , pwrdn , mode 1 a input capacitance (note 4) c in cs , wr , rd , pwrdn , mode 58 pf int , d0-d7, i sink = 20a 0.1 int , d0-d7, i sink = 400a 0.4 output low voltage v ol rdy, i sink = 1ma 0.4 v int , d0-d7, i source = 20a v dd -0.1 output high voltage v oh int , d0-d7, i source = 400a v dd -0.4 v floating-state current i lkg d0-d7, rdy 3 a floating capacitance (note 4) c out d0-d7, rdy 58 pf 2.5 5 v ss unipolar operation gnd v positive supply voltage v dd 3.0 3.6 v v dd = 3.6v 2.5 6 1.5 3 positive supply current i dd v dd = 3.0v 1.5 3.5 ma cs = rd = v dd , pwrdn = 0 a negative supply current i ss cs = rd = 0, pwrdn = v dd 15 0 a power-down v ss current cs = rd = v dd , pwrdn = 0 12 5 a power-supply rejection psr v dd = 3.3v 10% 1/16 1/4 lsb max152e/m, cs = rd = 0, pwrdn = v dd max152c, cs = rd = 0, pwrdn = v dd max152e/m, cs = rd = 0, pwrdn = v dd negative supply voltage bipolar operation (note 2) -3.6 -3.0 power-down v dd current (note 5) max152c, cs = rd = 0, pwrdn = v dd symbol min typ max note 1: accuracy measurements performed at v dd = 3.0v, unipolar mode. operation over supply range is guaranteed by power- supply rejection test. note 2: bipolar tests are performed with vref+ = +1.5v, vre f- = -1.5v, v ss = -3.0v. note 3: unipolar input range, v in = 3.0v p-p , wr-rd mode, v dd = 3.0v note 4: guaranteed by design. note 5: power-down current increases if control inputs are not driven to ground or v dd . electrical characteristics (continued) (unipolar input range, v dd = 3.0v to 3.6v, gnd = 0v, v ss = gnd, vref+ = 3.0v, vref- = gnd, specifications ar e given for rd mode (pin 7 = gnd), t a = t min to t max , unless otherwise noted.) 15 0 max152c/e/m logic inputs logic outputs power requirements downloaded from: http:///
_________________________________________________________________________________________ m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n 4 _______________________________________________________________________________________ parameter symbol conditions max152c/e t a = t min to t max min max max152m t a = t min to t max min max units wr pulse width t wr 0.6 10 0.66 10 0.8 10 s delay time between wr and rd pulses t rd 0.8 0.9 1.0 s rd pulse width t read1 400 500 600 ns t acc1 400 500 600 ns rd to int delay t ri 300 340 400 ns t cwr t rd < t intl , c l = 100pf 1.8 2.06 2.4 s conversion time (rd mode) t crd 2.0 2.3 2.6 s power-up time t up 0.9 1.2 1.4 s cs to rd , wr setup time t css 0 0 0 ns cs to rd , wr hold time t csh 0 0 0 ns cs to rdy delay t rdy c l = 50pf, r l = 5.1k to v dd 100 120 140 ns wr to int delay t intl c l = 50pf 0.7 1.45 1.6 1.8 rd pulse width t read2 wr-rd mode, t rd > t intl , determined by t acc2 (figure 5) 180 220 250 ns data access time (note 7) t acc2 180 220 250 ns wr to int delay t ihwr 180 200 240 ns data access time after int (note 7) t id stand-alone mode, c l = 100pf 100 130 150 ns data access time (rd mode) (note 7) t acc0 c l = 100pf t crd +100 t crd +150 ns rd to int delay (rd mode) t inth c l = 50pf 100 160 170 180 ns data hold time (note 8) t dh 100 130 150 ns t p 450 600 700 ns all grades t a = +25c min typ max conversion time (wr-rd mode) delay time between conversions data access time (note 7) wr-rd mode, determined by t acc1 (figure 6) wr-rd mode, t rd < t intl , c l = 100pf (figure 6) wr-rd mode, t rd < t intl , c l = 100pf (figure 5) t crd +130 s timing characteristics (unipolar input range, v dd = 3v, v ss = 0v, t a = +25c, unless otherwise noted.) (note 6) note 6: input control signals are specified with t r = t f = 5ns, 10% to 90% of +3.0v, and timed from a voltag e level of 1.3v. timing delays get shorter at higher supply voltages. see t he converson time vs. supply voltage graph in the typical operating characteristics to extrapolate timing delays at other power-supply voltages. note 7: see figure 1 for load circuit. parameter defined as the time required for the output to cross 0.66v or 2.0v. note 8: see figure 2 for load circuit. parameter defined as the time required for the data lines to change 0.5 v. stand-alone mode, c l = 50pf downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n ___________________________________________________ ______________________________________________ 5 1.6 0.4 -60 140 conversion tim e vs. am bient tem perature 0.6 1.4 temperature (c) t crd (normalized to value at +25c) 60 1.0 0.8 -20 20 100 1.2 v dd = 3.3v v dd = 3.6v v dd = 3.0v 1400 800 2.8 4.0 conversion tim e vs. supply voltage 900 1300 supply voltage (v) t crd (ns) 3.6 1100 1000 3.0 3.4 3.8 1200 3.2 8.0 4.0 1k 10k 100k effective bits vs. input frequency, wr-rd m ode input frequency (hz) effective bits 1m 7.5 7.0 6.5 6.0 5.5 5.0 4.5 v dd = 3.0v f sample = 400khz v in = 2.98vp-p t a = t min to t max 0 -120 0 200 signal-to-noise ratio frequency (khz) ratio (db) 120 -80 40 80 160 -40 -20 -100 -60 f in = 30.27 khz f sample = 400ksps snr = 48.2db 6 1 2.8 3.0 3.4 3.8 supply current vs. supply voltage 2 5 supply voltage (v) supply current (ma) 3.2 3.6 4 3 military cs = rd = 0v commercial +25c extended 5 0 120 160 240 32 0 error vs. power-up tim e 1 4 max186 - 5 t up (ns) error (lsbs) 200 280 3 2 v dd = 3.0v v dd = 3.6v __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (t a =+25c, unless otherwise noted). 0.7 2.8 3.8 norm alized tim ing vs. supply voltage 0.8 1.1 supply voltage (v) timing (normalized to v dd = 3.0v) 3.4 1.0 0.9 3.0 3.2 3.6 4.0 10,000 1 1 100k average power consum ption vs. conversion rate using pwrdn 10 1000 conversions/sec supply current (a) 1k 100 10 100 10k 1m v dd = 3.0v downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n 6 _______________________________________________________________________________________ pin name function 1 v in 2 d0 three-state data output (lsb) 3-5 d1-d3 three-state data outputs 6 wr /rdy 7 mode 8 rd 9 int 10 gnd ground 11 vref- 12 vref+ 13 cs 14-16 d4-d6 three-state data outputs 17 d7 three-state data output (msb) 18 pwrdn 19 v ss 20 v dd positive supply, +3v. analog input. range is vref- v in vref+. write control input/ready status output* mode selection input is internally pulled low with a 15a current source. mode = 0 activates read mode mode = 1 activates write-read mode* read input must be low to access data.* interrupt output goes low to indicate end of conversion.* lower limit of reference span. sets the zero-code voltage. range is v ss vref- < vref+. upper limit to reference span. sets the full-scale input voltage. range is vref- < vref+ v dd . chip-select input must be low for the device recognize wr or rd inputs. powerdown input reduces supply current when low. negative supply. unipolar: v ss = 0v, bipolar: v ss = -3v. ____________________pin de sc ript ion _______________d e t a ile d de sc ript ion conve rt e r ope ra t ion the max152 uses a half-flash conversion technique (see functional diagram ) in which two 4-bit flash adc sections achieve an 8-bit result. using 15 compara - tors, the flash adc compares the unknown input volt - age to the reference ladder and provides the upper 4 data bits. an internal digital-to-analog converter (dac) uses the 4 most significant bits (msbs) to generate the anal og result from the first flash conversion and a residu e volt- age that is the difference between the unknown inpu t and the dac voltage. the residue is then compared again with the flash comparators to obtain the lowe r 4 data bits (lsbs). the max152 is characterized for operation between +3.0v and +3.6v. conversion times decrease as the supply voltage increases. the supply current decre as- es rapidly with decreasing supply voltage. (see typical operating characteristics .) pow e r-dow n m ode in burst-mode or low sample-rate applications, the max152 can be shut down between conversions, reducing supply current to microamp levels (see typical operating characteristics ). a logic low on the pwrdn pin shuts the device down, reducing supply current to typically 1a when powered from a single 3v supply. a logic high on pwrdn wakes up the max152. a new conversion can be started within 900ns of the pwrdn pin being driven high (this includes both the power-up delay and the track/hold acquisition time). if power-down mode is not requi red, connect pwrdn to v dd . *see digital inferface section. data outputs data outputs c l 3k c l a. high-z to v oh b. high-z to v ol 3k v dd figure 1. load circuits for data-access time test data outputs 10pf 3k 10pf a. v oh to high-z b. v ol to high-z 3k v dd data outputs figure 2. load circuits for data-hold time test downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n _______________________________________________________________________________________ 7 once the max152 is in power-down mode, lowest sup- ply current is drawn with mode low (rd mode) due to an internal pull-down resistor at this pin. in add ition, for minimum current consumption, other digital inputs should remain high in power-down. refer to the reference section for information on reducing refer- ence current during power-down. ___________________digit a l i nt e rfa c e the max152 has two basic interface modes set by the status of the mode input pin. when mode is low, the converter is in the rd mode; when mode is high, the converter is set up for the wr-rd mode. re a d m ode (m ode = 0 ) in rd mode, conversion control and data access are controlled by the rd input (figure 3). the comparator inputs track the analog input voltage for the durat ion of t p . a conversion is initiated by driving rd low. with ps that can be forced into a wait state, hold rd low until output data appears. the p starts the conversion, waits, and then reads data with a single read instr uction. wr /rdy is configured as a status output (rdy) in rd mode, where it can drive the ready or wait input of a p. rdy is an open-collector output (with no inter nal pull-up) that goes low after the falling edge of cs and goes high at the end of the conversion. if not use d, the wr /rdy pin can be left unconnected. the int output goes low at the end of the conversion and returns h igh on the rising edge of cs or rd . writ e -re a d m ode (m ode = 1 ) figures 4 and 5 show the operating sequence for the write-read (wr-rd) mode. the comparator inputs track the analog input voltage for the duration of t p . the conversion is initiated by a falling edge of wr . when wr returns high, the 4 msbs' flash result is latched into the output buffers and the 4 lsbs' con ver- sion begins. int goes low, indicating conversion end, and the lower 4 data bits are latched into the outp ut buffers. the data is then accessible after rd goes low (see timing characteristics ). t up t css t p t csh t dh t read2 t rd d0-d7 rd wr cs pwrdn int valid data t intl t acc2 t wr figure 4. wr-rd mode timing (t rd > t intl ) (mode = 1) t up t css t p t csh t dh t read1 t rd rd wr cs pwrdn int valid data t inth t wr t acc1 t cwr t ri figure 5. wr-rd mode timing (t rd < t intl ), fastest operating mode (mode = 1) t up t css t rdy with external pull-up t p t csh t inth t dh t crd t acco d0-d7 rdy rd cs pwrdn int valid data figure 3. rd mode timing (mode = 0) downloaded from: http:///
m ax 1 5 2 a minimum acquisition time (t p ) is required from int going low to the start of another conversion ( wr going low). options for reading data from the converter include the following: u sing i nt e rna l de la y the p waits for the int output to go low before read- ing the data (figure 4). int goes low after the rising edge of wr , indicating that the conversion is complete and the result is available in the output latch. w ith cs low, data outputs d0-d7 can be accessed by pulling rd low. int is then reset by the rising edge of cs or rd . fa st e st conve rsion: re a ding be fore de la y an external method of controlling the conversion ti me is shown in figure 5. the internally generated delay t intl varies slightly with temperature and supply volt- age, and can be overridden with rd to achieve the fastest conversion time. rd is brought low after the ris- ing edge of wr , but before int goes low. this com- pletes the conversion and enables the output buffer s (d0-d7) that contain the conversion result. int also goes low after the falling edge of rd and is reset on the rising edge of rd or cs . the total conversion time is therefore: t cwr = t wr (600ns) + t rd (800ns) + t acc1 (400ns) = 1800ns. st a nd-alone ope ra t ion besides the two standard wr-rd mode options, stand- alone operation can be achieved by connecting cs and rd low (figure 6). a conversion is initiated by pulling wr low. output data can be read by either edge of the next wr pulse. +3 v, 8 -bit adc w it h 1 a pow e r-dow n 8 _______________________________________________________________________________________ t p t intl wr int new data t wr t ihwr t id old data d0-d7 figure 6. stand-alone mode timing ( cs = rd = 0) (mode = 1) vref- max152 v dd 0.1f v in vref+ v in + v in - gnd +3v 1 10 20 12 11 4.7f figure 7a. power supply as reference +3v 0.1 f 4 vref- max152 vref+ v in 8 1 3 7 0.1 f 4.7 f 2 6 gnd v dd 10 1 20 12 11 +2.5v 34.8k 3.01k lm10 v in + v in - figure 7b. external reference, +2.5v full scale +3v 0.1f 12 vref- max152 vref+ v in 10 1 20 11 0.1f 4.7f gnd v dd 0.1f v in- 1.2v v in + *current path must still exist from v in - to gnd. figure 7c. input not referenced to gnd +3v pwrdn c1 2.2f mtd3055el n max152 vref- v dd vref+ pwrdn max872 + figure 7d. an n-channel mosfet switches off the re ference load during power-down. downloaded from: http:///
____________ana log conside ra t ions re fe re nc e figures 7a-7c show some reference connections. vref+ and vref- inputs set the full-scale and zero- input voltages of the adc. the voltage at vref- defines the input that produces an output code of a ll zeros, and the voltage at vref+ defines the input t hat produces an output code of all ones. the internal resistance from vref+ to vref- may be as low as 1k , and current will flow through it even when the max152 is shut down. figure 7d shows how an n- channel mosfet may be connected to vref- to break this path during power-down. the fet should have a n on resistance < 2 with a 3v gate drive. although vref+ is frequently connected to v dd , this circuit uses a low current, low-dropout, 2.5v volta ge reference C the max872. since the max872 cannot continuously furnish enough current for the referen ce resistance, this circuit is intended for applicatio ns where the max152 is normally in standby and is turned on in order to make measurements at intervals greater tha n 20s. the capacitor c1 connected to vref+ is slowl y charged by the max872 during the standby period and furnishes the reference current during the short me asure- ment period. the 2.2f value of c1 is chosen so that its voltage drops by less than 1/2lsb during the conversion process. larger capacitors reduce the error still further. use ceramic or tantalum capacitors for c1. when vref- is switched, as in figure 7d, a new conv er- sion can be initiated after waiting a time equal to the power-up delay (t up ) plus the turn-on time of the n-chan- nel fet. bypa ssing a 4.7f electrolytic in parallel with a 0.1f ceram ic capacitor should be used to bypass v dd to gnd. these capacitors should have minimal lead length. the reference inputs should be bypassed with 0.1f capacitors, as shown in figures 7a-7c. i nput curre nt figure 8 shows the equivalent circuit of the conver ter input. when the conversion starts and wr is low, v in is connected to sixteen 0.6pf capacitors. during this acqui- sition phase, the input capacitors charge to the in put volt- age through the resistance of the internal analog s witches. in addition, about 12pf of stray capacitance must b e charged. the input can be modeled as an equivalent rc network (figure 9). as source impedance increases, the capacitors take longer to charge. the typical 22pf input capacitance allows source re sis- tance as high as 2.2k without setup problems. for larg- er resistances, the acquisition time (t p ) must be increased. m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n _______________________________________________________________________________________ 9 r on r in v in 1 c v in max152 figure 8. equivalent input circuit 4k r v in 1 12pf v in max152 10pf figure 9. rc network equivalent input model downloaded from: http:///
m ax 1 5 2 conve rsion ra t e the maximum sampling rate (f max ) for the max152 is achieved in the wr-rd mode (t rd < t intl ) and is cal- culated as follows: signa l-t o-n oise ra t io a nd effe c t ive n um be r of bit s signal-to-noise plus distortion ratio (sinad) is th e ratio of the fundamental input frequency's rms amplitude to the rms amplitude of all other adc output signals. the output band is limited to frequencies above dc and below one-half the adc sample rate. the theoretical minimum a/d noise is caused by quan - tization error, and results directly from the adc's reso- lution: snr = (6.02n + 1.76)db, where n is the numb er of bits of resolution. therefore, a perfect 8-bit adc can do no better than 50db. the fft plot ( typical operation characteristics ) shows the result of sampling a pure 30.27khz sinusoid at a 400khz rate. this fft plot of the output shows the out- put level in various spectral bands. the effective resolution, or "effective number of b its," the adc provides can be measured by transposing the equation that converts resolution to snr: n = (sin ad - 1.76)/6.02 (see typical operating characteristics ). t ot a l h a rm onic dist ort ion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal (in the fr equen- cy band above dc and below one-half the sample rate ) to the fundamental itself. this is expressed as: where v 1 is the fundamental rms amplitude, and v 2 to v n are the amplitudes of the 2nd through nth harmonics . spurious-fre e dyna m ic ra nge spurious-free dynamic range is the ratio of the fun da- mental rms amplitude to the amplitude of the next largest spectral component (in the frequency band above dc and below one-half the sample rate). usually the next largest spectral component occurs at some harmonic of the input frequency. however, if the adc is exceptionally linear, it may occur only at a ran- dom peak in the adc's noise floor. see "signal to n oise ratio" plot in typical operating characteristics . thd 20 log (v 2 2 v 3 2 v 4 2 v n 2 ) v 1 = ++++ ? ? l f 1 tttt e.g. at t 25 c, v 3.0v: f max 1 600ns 800ns 300ns 450ns f 465khz where t write pulse width t delay between wr and rd pulses t = rd to int delay t = delay time between conversons. max wr rd ri p ad d max wr rd ri p = +++ =+ =+ = +++ == = +3 v, 8 -bit adc w it h 1 a pow e r-dow n 10 ______________________________________________________________________________________ downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n ______________________________________________________________________________________ 11 ___________________chip topogra phy ___________________________________________________ _____pa c k a ge i nform a t ion d7d6 d5 d4 d3 d2 d1 d0 pwrdncs v in v ss v dd rd int gnd vref- vref+ mode wr/rdy 0.098" 2.49mm 0.104" 2.64mm transistor count: 1856 substrate connected to v dd max152 c a a2 e1 d e e a e b a3 b1 b dim a a1 a2 a3 b b1 c d d1 e e1 e e a e b l a min C 0.015 0.125 0.055 0.016 0.050 0.008 1.015 0.040 0.300 0.240 C 0.115 0? max 0.200 C 0.150 0.080 0.022 0.065 0.012 1.045 0.070 0.325 0.280 0.400 0.150 15? min C 0.38 3.18 1.40 0.41 1.27 0.20 25.78 1.02 7.62 6.10 C 2.92 0? max 5.08 C 3.81 2.03 0.56 1.65 0.30 26.54 1.78 8.26 7.11 10.16 3.81 15? inches millimeters 2.54 bsc7.62 bsc 0.100 bsc0.300 bsc a1 l d1 e 21-333a 20-pin plastic dual-in-line package a downloaded from: http:///
m ax 1 5 2 +3 v, 8 -bit adc w it h 1 a pow e r-dow n 12 ______________________________________________________________________________________ __________________________________________pa c k a ge i nform a t ion (c ont inue d) l dim a a1 b c d e e h h l a min 0.093 0.004 0.014 0.009 0.496 0.291 0.394 0.010 0.016 0? max 0.104 0.012 0.019 0.013 0.512 0.299 0.419 0.030 0.050 8? min 2.35 0.10 0.35 0.23 12.60 7.40 10.00 0.25 0.40 0? max 2.65 0.30 0.49 0.32 13.00 7.60 10.65 0.75 1.27 8? inches millimeters a 20-pin plastic small-outline package h e d e a a1 c h x 45? 0.127mm 0.004in. b 1.27 bsc 0.050 bsc 21-334a downloaded from: http:///

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